1. Field of the Invention
This invention relates generally to digital electronic systems. More particularly, this invention relates to techniques for efficiently transferring information in digital electronic systems.
2. Description of the Related Art
In a generalized multi-device digital electronic system, there can be multiple aster and slave devices which are connected by an interconnect structure, as shown in FIG. 1. Wires between the components form the interconnect. Transport of information over the interconnect occurs from transmitter to receiver, where the master or the slave components can act as either transmitter or receiver.
One particularly interesting case is when the slave is a memory device and there is a single master, as shown in FIG. 2. Because of the high occurrence of read operations in typical memory reference traffic, an important case is the transmission of control information from master to slave and the return transmission of read data from slave to master. The round trip delay forms the read latency.
In a pipelined system, total delay to perform an operation is divided into clock cycles by dividing the entire datapath into separate pipe stages. In a pipelined memory system, total read latency is also divided into clock cycles. As operating frequency increases, delay variations from both the interconnect and components are exposed. These delay variations can cause logical device-to-device conflicts which make the operation pipeline less efficient. It is thus desirable to compensate for these timing variations, which can occur depending on the position of the memory parts on the channel and internal delays in the memory devices.
Before discussing the sources of timing variation in a memory system, some background information on the structure and operation of memory cores is provided.
Memory Structure and Operation
In this section memory operations are defined. FIG. 3 illustrates a memory with a memory core and a memory interface. The memory interface interacts with an interconnect structure. The following discussion expands upon the generic memory elements of FIG. 3 to identify separate structural elements and to discuss the memory operations and memory interactions with the interconnect.
General Memory Core
In this subsection the structure of memory cores into rows and columns is illustrated and the primitive operations of sense, precharge, read, and write are introduced.
A simple memory core typically consists of a storage array, column decoder, row decoder, and sense amplifiers, as shown in FIG. 4. The interface 100 to a memory core generally consists of a row address 101, column address 103, and data path 102. The storage array, shown in FIG. 6, is organized into rows and columns of storage cells, each of which stores one bit of information. Accessing the information in the storage array is a two step process. First, the information is transferred between the storage array and the sense amplifiers. Second, the information is transferred between the sense amplifiers and the interface via connection 100.
The first major step, transferring information between the storage array and the sense amplifiers, is called a "row access" and is broken down into the minor steps of precharge and sense. The precharge step prepares the sense amplifiers and bit lines for sensing, typically by equilibrating them to a midpoint reference voltage. During the sense operation, the row address is decoded, a single word line is asserted, the contents of the storage cell is placed on the bit lines, and the sense amplifier amplifies the value to a full rail state, completing the movement of the information from the storage array to the sense amplifiers. An important observation is that the sense amps can also serve as a local cache which stores a "page" of data which can be more quickly accessed with column read or write accesses.
The second major step, transferring information between the sense amplifiers and the interface, is called a "column access" and is typically performed in one step. However, variations are possible in which this major step is broken up into two minor steps, e.g. putting a pipeline stage at the output of the column decoder. In this case the pipeline timing has to be adjusted.
From these two major steps, four primary memory operations result: precharge, sense, read, and write. (Read and write are column access operations.) All memory cores support these four primary operations or some subset of these operations. As later sections describe, some memory types may require additional operations that are required to support a specific memory core type.
As shown in FIG. 5, memory cores can also have multiple banks, which allow simultaneous row operations within a given core. Multiple banks improve memory performance through increased bank concurrency and reduced bank conflicts. FIG. 5 shows a typical core structure with multiple banks. Each bank has its own storage array and can have its own set of sense amplifiers to allow for independent row operations. The column decoder and datapath are typically shared between banks.
FIG. 6 shows the generic storage array structure. As shown, the word line (106) accesses a row of storage cells, which in turn transfers the stored data on to the bit lines (107). While the figure shows a pair of bit lines connected to each storage cell, some core organizations may require only one bit line per cell, depending on the memory cell type and sensing circuits.
The general memory core just described provides the basic framework for memory core structure and operations. However, there are a variety of core types, each with slight differences in structure and function. The following three sub-sections describe these differences for each major memory type.
Dynamic RAM (DRAM)
This section describes the structure and primitive operations for the conventional DRAM core. The structure of a conventional DRAM core is shown in FIG. 7. Like the generic memory core in FIG. 4, the conventional DRAM structure has a row and column storage array organization and uses sense amplifiers to perform row access. As a result, the four primary memory operations, sense, precharge, read and write, are supported. The figure shows an additional "column amplifier" block, which is commonly used to speed column access.
The core interface 100 consists of the following signals: row address 101, column address 103, data I/O bus 106, row control signals 107 (these signals are defined in detail further in this section), and column control signals 108 (these signals are defined in detail further in this section).
FIG. 8 shows a conventional DRAM core with multiple banks. In this figure, the row decoder, column decoder, and column amplifiers are shared among the banks. Alternative organizations can allow for these elements to be replicated for each bank, but replication typically requires larger die area and thus greater cost. Cheap core designs with multiple banks typically share row decoders, column decoders and column datapaths between banks to minimize die area.
Conventional DRAM cores use a single transistor (1T) cell. The single transistor accesses a data value stored on a capacitor, as shown in FIG. 9. This simple storage cell achieves high storage density, and hence a low cost per bit, but has two detrimental side effects. First, it has relatively slow access time. The relatively slow access time arises because the passive storage capacitor can only store a limited amount of charge. Row sensing for conventional DRAM takes longer than for other memory types with actively-driven cells, such as SRAM. Hence, cheap DRAM cores generally result in slow row access and cycle times. Another problem is that cell refresh is required. Since the bit value is stored on a passive capacitor, the leakage current in the capacitor and access transistor result in degradation of the stored value. As a result, the cell value must be "refreshed" periodically. The refresh operation consists of reading the cell value and rewriting the value back to the cell. These two additional memory operations are named refresh sense and refresh precharge, respectively. In traditional cores, refresh sense and refresh precharge were the same as regular sense and precharge operations. However, with multiple bank cores, special refresh operations are advantageous to enable dedicated refresh circuits and logic to support multibank refresh.
FIG. 10 shows details of a bit slice of a typical row datapath, and FIG. 11 shows the timing diagram of a precharge and sense operation. To perform a row access, the bit lines and sense amplifiers must first be precharged, typically to the Vdd/2 midpoint. The row precharge time, tRP, is shown in FIG. 11.
To perform a sense operation, the row decoder drives a single word line to turn on access transistors to a row of memory cells. The charge on the storage capacitor transfers to the bit line, slightly changing its voltage. The sense amplifier detects this small voltage change and drives the bit lines to full rail (Vdd and Gnd). The wordline must be held high a significant portion of the time period of tRAS,min to complete the sensing operation. At some time before the bit lines reach full rail, a column read or write access can begin. The time between the start of the sense operation and the earliest allowable column access is TRCD, row to column access delay.
The total time to perform both precharge and sense is tRC, the row cycle time, and is a primary metric for core performance. Table 1 shows typical DRAM row timing values.
TABLE 1 Typical DRAM Row Timing Parameters Symbol Description Value Units tRP Row precharge time 20 ns tRCD Row to column delay 26 ns tRC Row cycle time 80 ns tRAS, min Minimum row active time 60 ns
It is important to note that memory device timing parameters can vary widely across various device designs, manufacturing processes, supply voltage, operating temperature, and process generations. In order for the memory architecture to be widely usable, it is very important for the protocol to be able to support these variable row and column timings.
FIG. 10 shows a common cell organization which alternates cell connections between wordlines. This leads to a dense packing of cells and also allows the sense amplifier to use the voltage on the unused bitline as a reference for differential bit line sensing.
Separate PRECH and SENSE control can be used at the core interface. Traditional cores use a single control signal, commonly called RAS, and use the rising and falling edges to distinguish between sense and precharge. Separated PRECH and SENSE signals, together with a separate bank address for sense and precharge, support cores with pipelined precharge and sense operations occurring in multiple banks.
The row sensing power includes the power to decode the row address, drive the wordline high, and turn on the sense amplifiers, which must drive the bit lines from Vdd/2 to Vdd and Gnd. Thus, a significant portion of row sense power is proportional to the number of sense amplifiers that are turned on (i.e., the page size).
FIG. 12 shows an example of row access timing diagram for DRAMs with multiple banks. The period t.sub.SS specifies the minimum delay between sense operations to different banks. Similarly, the period t.sub.PP specifies the minimum delay between precharge operations to different banks.
FIG. 13 is a more detailed diagram of a typical DRAM column datapath. The output of the column decoder, which may be placed in a register for pipelined designs, drives a single column select line, which selects some fraction of outputs from the sense amplifiers. The selected sense amplifiers then drive the data on to the column I/O wires. To speed column access time, the column I/O lines are typically differential and sensed using differential column amplifiers, which amplify small voltage differences on the column I/O wires and drive the data I/O bus to the interface. The width of the column I/O bus sets the data granularity of each column access, also known as CAS block granularity.
The data I/O can either be bidirectional, in which write and read data are multiplexed on the same bus, or unidirectional, in which write and read data have separate buses. FIG. 13 shows unidirectional data I/O.
Column access power consists of the power to decode the column address, drive the column select line, turn on the column amplifiers, and drive the column I/O wires. Column power is roughly proportional to the column cycle frequency and the width of the column I/O datapath.
Some DRAM cores also include the ability to mask write data, so that some bits or bytes of the datapath are not written depending on the mask pattern. Typically, the mask pattern is delivered to the column amplifier write circuit, which inhibits the write data appropriately.
A timing diagram for a column read operation is shown in FIG. 14. The key timing parameters of the column read access are:
tPC, column cycle time: the minimum cycle time of a column access. This parameter determines how fast data can be cycled to and from the memory core. The CAS block granularity divided by tPC equals the core data bandwidth. PA0 tCLS, COLLAT setup to COLCYC: the minimum set-up time of latching the column address to the rising edge of COLCYC, when data access from the sense amplifiers starts. PA0 tDAC, column read access delay: the delay from the rising edge of COLCYC to when READDATA is valid at the interface. PA0 tCAS: the minimum time that COLCYC stays high. This parameter sets the maximum time it takes to transfer data from the sense amplifiers to the column amplifiers and determines when column precharge can start. PA0 tCP, column precharge: the minimum time that COLCYC stays low. This parameter sets the maximum time it takes to precharge the column I/O wires. PA0 tCPS, COLCYC low setup to row precharge: the minimum set up time that COLCYC stays low before row precharge begins. This parameter is important since tCAS+tCPS determines when a row precharge operation can begin relative to the start of a column operation. PA0 tDOH, data output hold time: tDOH is the minimum hold time of READDATA after the next COLCYC rising edge. Note: tPC-tDAC+tDOH determines the READDATA minimum valid window at the core interface. PA0 tASC, column address setup: the minimum column address set up time before COLLAT rising edge. PA0 tCAH, column address hold: the minimum column address hold time after COLLAT rising edge. Note: tASC+tCAH determine the minimum column address valid window that must be observed to perform a column operation to the core. PA0 tCLL, COLLAT low: the minimum time that COLLAT stays low. PA0 tCLH, COLLAT high: the minimum time that COLLAT stays high. PA0 tDS, WRITEDATA setup: the minimum WRITEDATA setup time before the rising edge of COLCYC. PA0 tDH, WRITEDATA hold: the minimum WRITEDATA hold time after the falling edge of COLCYC. PA0 tWES, WMASK setup: the minimum set up time for a write mask before the rising edge of COLCYC. PA0 tWEH, WMASK hold: the minimum hold time for a write mask after the falling edge of COLCYC. Note: tWES+tCAS+tWEH determines the minimum WMASK valid window that must be observed to perform a write mask operation to the core.
A timing diagram for column write operation is shown in FIG. 15. Many timing parameters, which include tPC, tCAS, tCP, tCLS, tCPS, tCLL, tCLH, tASC and tCAH, are the same as those for column read. Additional key timing parameters of the column write access are
Note: tDS+tCAS+tDH determines the minimum WRITEDATA valid window that must be observed to perform a write operation to the core.
Table 2 shows typical DRAM column timing values.
TABLE 2 Typical DRAM Column Timing Values Symbol Description Value Units tPC Column cycle time 10 ns tCAS COLCYC high 4 ns tCP COLCYC low 4 ns tCLS COLLAT to COLCYC setup 2 ns tDAC READDATA valid from COLCYC rising 7 ns tCPS COLCYC low setup time to row precharge 1 ns tASC COLADDR setup to COLLAT rising 0 ns tCAH COLADDR hold from COLLAT rising 5 ns tDOH READDATA hold from next COLCYC rising 3 ns tDS WRITEDATA hold from COLCYC falling 1 ns tDH WRITEDATA hold from COLCYC falling 1 ns tWES WMASK setup to COLCYC rising 2 ns tWEH WMAST hold from COLCYC falling 0 ns
It is important to note that DRAM timing parameters can vary widely across various manufacturing processes, supply voltage, operating temperature, and process generations. In order for the memory architecture to be widely usable, it is very important for the DRAM protocol to be able to support these variable row and column timings.
Typical column cycle times and access times greatly depend on the type of sense amplifier circuit, since the sense amplifier actually drives the data on to the column I/O wires. Increased speeds can be achieved by using more transistors in the sense amplifier circuit to improve drive capability, but this greatly increases the die area and cost since the sense amplifier circuit is heavily replicated. Thus, the desire to minimize die area for commodity DRAMs inhibits the further reduction of column access speeds.
Static RAM (SRAM)
SRAM shares a similar core structure and functional blocks as DRAM. Like DRAM, access is performed in a similar two step process. First, in the sense operation, the information is transferred between the storage array and the sense amplifiers. Second, in the column access operation, the information is transferred between the sense amplifiers and the interface. Also, similar to DRAM, the bitlines must be precharged before sensing occurs, although a typical precharge value is Vdd, not Vdd/2.
The key difference lies in the storage cell. In an SRAM, data is stored statically, typically using a circuit of several transistors. A typical SRAM cell is shown in FIG. 16. The SRAM of FIG. 16 uses cross-coupled CMOS inverters to store a single data bit. A word line turns on access transistors, which connect the cell circuit to differential bit lines. Unlike a DRAM cell, the SRAM cell circuit actively drives the stored value on to the bit lines, thus resulting in faster access time. The static nature of the SRAM cell eliminates the need for cell refresh. However, the static cell also uses more transistors and takes up much more area than a DRAM cell. The four primitive operations of an SRAM are sense, precharge, read and write.
Read-Only Memory
Read-only memory cores store information according to an electrical connection at each cell site which joins rows to columns. Typically, a single transistor forms the electrical connection at each cell site. A simple ROM array is shown in FIG. 17.
There are a variety of ROM cell types, including erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash ROM, and mask programmable ROM. Their differences lie in the type of transistor used at the cell site. However, all ROM types share the common 2-D storage array organization, which requires a row and column decode of the address for each data access.
Unlike SRAMs or DRAMs, not all ROMs have sense amplifier circuits. Sense amplifiers are only used in some ROMs which require fast access times. For these ROMs, the primitive operations are sense, precharge and read.
For slower ROMs that do not use sense amplifiers, the data values are directly driven from the cell to output amps which drive the interface. For these ROMs, the single primitive operation is read.
Summary of Memory Operations
Table 3 summarizes the primary operations for each memory type.
TABLE 3 Memory Operations Conventional DRAM SRAM ROM.sup.a data = read(device, bank, data = read)device, data = read(device, column) bank, column) bank, column) write(device, bank, write(device, bank, column, data, mask) column, data, mask) precharge(device, bank) precharge(device, precharge(device, bank) bank) sense(device, bank, row) sense(device, bank, row) refresh precharge (device, bank)&lt;multi-bank&gt; refresh sense(device, bank, row)&lt;multi-bank&gt; .sup.a Some ROM organizations without sense amplifiers may not require precharge and sense operations. For these types, data = read(device, bank, row, column).
Memory Operation Sequencing
Based on the operations defined in the previous section, this section describes the allowable sequences of operation for various memory types.
Operation Sequencing for Memory Cores with Sense Amp Caches
The composition of the operations cannot be arbitrary. With memory cores that use sensing to speed row access, such as conventional DRAMs and SRAMs, a bank must be in a sensed state in order to do read or write operations. Furthermore, the bank must be precharged in order to perform a sense operation. As a result, these cores must follow the pattern shown in FIG. 18 with respect to each bank's state, which can be either sensed ("open") or precharged ("closed").
Although all the operation sequences implied by FIG. 18 are allowed, they do not all have equal utility. The application that uses the memory exhibits a characteristic access pattern (a.k.a. reference pattern) which ultimately determines which operation sequences are most useful. These operational sequences can then be optimized through implementation or protocol design to maximize performance and minimize power and area.
Generally, an application will attempt to operate a sense amp memory core in a cached or uncached manner, depending upon the expected locality of reference from one application access to another. Combinations of these approaches are possible, but supporting arbitrary combinations can be an expensive proposition, resulting in either reduced performance or large resource usage both internally to the DRAM as well as externally in the interconnect.
Operating the memory in an uncached manner means that the bank state is closed between application accesses. In other words, the last memory operation performed on that bank is a precharge. In such an operating manner, each application access typically consists of the sequence: sense, series of reads and/or writes, precharge. Uncached usage assumes low reference locality, i.e. subsequent memory access will likely not be located in the same row.
Operating the memory in a cached manner means that the bank state is open between application accesses. In other words, the last memory operation performed on that bank is a sense, read, or write. Cached usage assumes high reference locality, i.e. subsequent memory access will likely be located in the same row. Generally, sense will not be the last memory operation performed since that implies that no useful work was done on behalf of the last application access. However, there are prefetching schemes which may have the last application access perform a sense with no corresponding read or write.
When the bank state has been left open, the following operation can be read, write, or precharge. If it is a read or write, we call this a hit operation, since the row which was left cached in the bank must have been the proper row for the following operation. If it is a precharge, the correct row was not left cached in the bank, so the controller must apply a precharge and sense sequence in order to move the correct row into the bank. We call this type of access a miss operation.
When operating the DRAM in a cached manner, each application access typically consists of the sequence "series of reads and/or writes" (hit) or the sequence "precharge, sense, series of reads and/or writes" (miss).
Since the precharge and sense operations take time and consume power, the optimal strategy for operating the DRAM depends upon the reference characteristics of the application. In the present invention either manner of operation, and mixed manners of operation, are supported.
Other Variations
FIG. 18 shows the operation sequencing for a generic memory core with sense amp caches. Variations of this diagram for different memory cores are also possible and are described in this section.
FIG. 19 shows operation sequencing for a DRAM, which is the same as that shown in FIG. 18, except for the addition of the refresh sense and refresh precharge operations.
FIG. 20 shows an operation sequence for a common class of SRAMs whose sense amps only hold enough data for one read or write access. Note that transition 202, while possible, is not useful since it does not perform any useful work on behalf of the last application access. Also note that writes can occur after either precharge or sense, since the sense amplifiers in SRAMs are only used for read operations. FIG. 21 shows an operation sequence for read-only memories with sense amps. Typically, sense amps only hold enough data for one read access. Note that transition 202, while possible, is not useful since it does not perform any useful work on behalf of the last application access.
Sources of Timing Variation
There are several sources of timing variation in a memory system. One source is the interconnect, also referred to as the channel. With a sufficiently high clock frequency and a long channel, the signal propagation delay of the wire is greater than the bit time. (Here the period of the bit rate is defined as the time it takes to transfer one bit; in the following examples, it is assumed that a bit is transferred on every clock edge, so the bit rate is 2.times. the clock frequency.) As a result, the interconnect delay varies as a function of physical position on the channel, as FIG. 22 illustrates. Note that the clock edges vary in time depending on the observation position. For this particular clock topology, the interconnect has both 15 transmit and receive clocks going in opposite directions, and FIG. 23 illustrates that the difference between transmit and receive clocks at a given position and time varies more than one clock cycle. It is also important to note that the interconnect delay for a given component doesn't change once its position is fixed.
Another source of timing variation originates from the memory device itself. FIG. 3 shows a representation of a memory device with an interface and memory core. Internal delays in the core can vary from device to device due to process variations, circuit design differences, as well as variations in operation conditions that affect voltage and temperature.
A memory core has four primary operations: precharge, sense, read, and write. Variations can occur in all components of core timing, which include the timing of row operations (sense and precharge), column operations (read and write) and interactions between row and column operations.
Row timing is characterized by the timing parameters in Table 1 and illustrated in the timing diagram in FIG. 11 (row timing). The row precharge time, tRP, is the time it takes to precharge the sense amplifiers and bitlines inside a memory bank in the core. A bank must be precharged before a sense operation can occur. The minimum time between the start of a sense operation and the start of a precharge operation is tRAS,min. The minimum time between sense operations to the same memory bank is the row cycle time, tRC.
Table 2 shows the basic column timing parameters, which are illustrated in the read and write timing diagrams in FIG. 14 and FIG. 15. tCAC is the delay between the latching of the column address and the delivery of read data to the core output. tCAC has two components: tCLS and tDAC. tCLS is the time between the rising edge of COLLAT (when column address is latched) and the rising edge of COLCYC (when data access from the sense amplifiers starts). tDAC is the time between the rising edge of COLCYC and when read data is delivered to the core output. tPC is the column cycle time, i.e. the minimum time between column operations.
The interactions between row and column operations are characterized by the timing parameters tRCD and tCPS and are illustrated in FIG. 11, FIG. 14 and FIG. 15. tRCD is the row to column delay and represents the time between the start of a sense operation and column operation (rising edge of COLCYC). tCPS is the column precharge to row precharge time and represents the time between the start of the column precharge (falling edge of COLCYC) and the start of the row precharge operation.
All these core timings can vary widely across manufacturing processes, process generations, circuit designs, supply voltage fluctuations, and operating temperature. Furthermore, these core timing variations combine with interconnect delay variations to form accumulative system timing variations from device to device.
Motivation for Timing Variation Control
In a pipelined memory system, it is desirable to adjust for or control device-to-device timing variations in order to optimize efficiency in the pipeline so that data bandwidth is maximized, particularly for read operations. The goal is to achieve a fully packed data interconnect when data is being transferred from transmitter to receiver, as illustrated in FIG. 24. As described earlier, either the master or slave can act as the transmitter or receiver; FIG. 24 illustrates a packed channel for either case.
Another desire is to minimize latency. For instance, for a device with a given tRCD, it would be desirable to provide enough fine-grain timing control between the row and column commands so that the delivery of the sense and column core control signals has an offset that closely matches tRCD. Any additional delay between the two commands would result in greater access latency.
Another desire is to minimize complexity. Timing adjustments can be done at either the transmitter or receiver. Since it is very desirable to keep the cost low, all mechanisms that perform timing adjustments, particularly in the memory devices, should have minimum complexity to keep die area and cost as low as possible.
Prior Art
Traditional memory systems use a two-dimensional device topology in which the data signals and control/address signals are orthogonal to each other, as illustrated in FIG. 25. Because of the different trace lengths, capacitive loadings, and unmatched signal impedances, the propagation delay for data and control/address signals differ significantly. Furthermore, device timing also varies between different parts. To account for this, memory controllers typically assume the worst possible interconnect and device timings, so all timing variations are handled by a fixed constant where the controller specifies how fast parts must be and all parts plugged into that system must meet those minimum timings. Unfortunately, it is sometimes difficult to know what the exact worst case will be. Furthermore, with this approach, the memory controller will always operate at the speed of the slowest possible part and interconnect rather than adjusting for the actual speed of the devices or interconnect in a given system. These systems initialize without a boot time procedure that examines the actual device performance of the installed parts.
In many existing synchronous memory systems, the interconnect delay is limited to a single clock cycle, so no interconnect delay compensation is needed. In some existing memory devices, variations in row timing, specifically tRAS,min, tRP, and tRCD, are "internally timed", i.e. row timing delays are handled with internal counters and programmable registers, which store cycle counts to match core timing. Some core timing, such as tCPS, is handled as a fixed design constant.
In some existing memory devices, variations in column read and write delay are handled by a single delay value that is programmable by changing the value in a register. The delay and range of the register are only designed to handle variations in device timing and not interconnect timing. Furthermore, a single delay value is used to cover multiple column read latency components, such as tCLS and tDAC. For example, in one implementation, a register specifies the number of clock cycles between the column control and the column read data, as shown in FIG. 26.
Both of these techniques have their costs and benefits. The all encompassing delay provides a simple control model to the application that does not vary with internal memory device implementation details. However, this requires the memory device to decode for itself how the programmed delay should be used. This can be a very difficult problem since the delay of any one device is not known at design time. A further complication is that the period of the clock during operation is not known, even at final test time when the device delays can be measured. Simple methods for solving this problem are not obvious. Methods involving division of an internal memory device delay by the clock period are not considered simple.
In some existing memory devices, fine timing control is limited due to the overloading of the interconnect control resources. FIG. 27 shows the interconnect structure of one such device, in which all row and column commands are issued over the same command bus. Also, the single address bus is shared for row and column operations. The row timing (tRP and tRAS,min) and row-to-column timing (tRCD, tCPS) variations are handled by adjusting the placement of control information over a single control bus resource. Because of conflicts, the overloading of both row and column commands on a single resource often limits the ability to perform fine timing control that optimally places row and column control to match actual device timings, as illustrated in FIG. 28. Because sense, precharge, read and write commands are issued over the same command bus, the resource quickly becomes overloaded, especially when commands are issued to many banks concurrently. In this figure, for instance, the separation between the precharge and sense to bank b is forced to be two cycles because of the write command to bank a, even though the device may have allowed a separation of one cycle.
In summary, existing memory devices have several inadequacies that limit optimal timing compensation in a high-speed pipelined memory system. First, existing devices are not designed to compensate for multicycle interconnect delay variation. Second, existing devices have a single shared interconnect control and/or address resource, which can limit the ability to have control over row timing and row-to-column timing variation when control information is packetized (occupies multiple cycles) and these parameters are not "internally timed". Third, timing variation of column access latency is typically controlled by a single number and not partitioned into the fundamental delay components that make up the column access latency in the core. Fourth, the column access to row precharge delay (tCPS) is considered a fixed constant in the device and must be compensated by adjusting the timing of external control information. Finally, variations in column cycle time must be compensated by adjusting the timing of external control information.